The present invention generally relates to memory architecture, and more specifically, to memory arrays.
With every new generation of processors, the number and density of memory cells increases. As a consequence, the probability of defective memory cells and/or connections between the memory cells usually increases as well. Memory cells may be organized in memory arrays, wherein each memory cell is connected to a bitline and a wordline.
In order to address the problem of defective memory cells and/or connections to and between the memory cells, redundant bitlines and/or wordlines connected to additional memory cells may be provided. In case a memory cell or interconnection of a certain bitline/wordline is defective, the redundant bitline/wordline may be used instead and the defective bitline/wordline may be ignored. Engineers continue to face challenges in designing usable redundancy systems for memory arrays.